Enclosure not stated · 3 knobs
DE-80
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- Delay· Delay Echo and Samplers
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- Delay Echo and Samplers
Schematic
The schematic is the archived file. Open it at Experimentalists Anonymous, or browse its folder.
Parts list 51 rows
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Check before you build · 5 values the reader of this schematic was not sure of
- Unlabelled filter-stage transistor assumed 2SC1815 like its neighbours
- Z reference electrolytic: no value printed
- Two trimmers have no value printed
- Reconstruction-filter cap read 0.022 where the matching anti-alias cap reads 0.0022; drawn that way
- Diode under the LED may be a zener
| Ref | Value | Normalized | Type | Notes |
|---|---|---|---|---|
| Resistors 25 | ||||
| ×1 | 1M | 1M | input pulldown; read from the schematic by eye | |
| ×1 | 470K | 470k | input buffer bias; read from the schematic by eye | |
| ×1 | 10K | 10k | input buffer emitter; read from the schematic by eye | |
| ×1 | 4K7 | 4.7k | IC1 input network; read from the schematic by eye | |
| ×3 | 33K | 33k | IC1 input, feedback and pin 3 bias; read from the schematic by eye | |
| ×1 | 2K2 | 2.2k | dry path; read from the schematic by eye | |
| ×3 | 12K | 12k | anti-alias and reconstruction filters; read from the schematic by eye | |
| ×13 | 10K | 10k | filter stages, emitters, NE570 and MN3101 networks; read from the schematic by eye | |
| ×4 | 47K | 47k | filter stages and MN3005 output pullup; read from the schematic by eye | |
| ×2 | 22K | 22k | NE570 input, MN3101 clock; read from the schematic by eye | |
| ×1 | 39K | 39k | NE570 feedback; read from the schematic by eye | |
| ×1 | 15K | 15k | into MN3005; read from the schematic by eye | |
| ×1 | 220K | 220k | MN3005 bias trimmer; read from the schematic by eye | |
| ×1 | 22K | 22k | IC1 mix feedback; read from the schematic by eye | |
| ×1 | 150K | 150k | repeat; read from the schematic by eye | |
| ×2 | 100K | 100k | IC1 pin 5 bias and output pulldown; read from the schematic by eye | |
| ×1 | 330 | 330 | output; read from the schematic by eye | |
| ×3 | 33K | 33k | expander feedback and JFET drain/source bias; read from the schematic by eye | |
| ×1 | 47K | 47k | flip-flop; read from the schematic by eye | |
| ×1 | 470K | 470k | flip-flop; read from the schematic by eye | |
| ×2 | 1M | 1M | flip-flop; read from the schematic by eye | |
| ×1 | 2K2 | 2.2k | LED; read from the schematic by eye | |
| ×1 | 4K7 | 4.7k | flip-flop to bypass switch; read from the schematic by eye | |
| ×2 | 100 | 100 | supply filter; read from the schematic by eye | |
| ×2 | 33K | 33k | Vref divider; read from the schematic by eye | |
| Capacitors 13 | ||||
| ×2 | 0.022uF | 22n | input coupling; reconstruction filter (drawn 0.022); read from the schematic by eye | |
| ×6 | 0.01uF | 10n | IC1 input, filter stages, flip-flop; read from the schematic by eye | |
| ×1 | 0.001uF | 1n | IC1 feedback; read from the schematic by eye | |
| ×2 | 0.0022uF | 2.2n | anti-alias filter; MN3005 input; read from the schematic by eye | |
| ×2 | 0.012uF | 12n | filter stages; read from the schematic by eye | |
| ×3 | 150P | 150p | filter stages and MN3101 clock; read from the schematic by eye | |
| ×6 | 0.047uF | 47n | NE570 output, to Mix, IC1 pin 5 network (2), JFET gate, flip-flop; read from the schematic by eye | |
| ×4 | 220P | 220p | NE570 (3), IC1 feedback; read from the schematic by eye | |
| ×5 | 10uF | 10u | electrolytic: input buffer out, compressor in, NE570 network (2), MN3005 pin 8; read from the schematic by eye | |
| ×5 | 1uF | 1u | electrolytic: NE570 pins 16 and 1, wet output, IC1 output, expander output; read from the schematic by eye | |
| ×1 | 220uF | 220u | electrolytic, supply; read from the schematic by eye | |
| ×1 | 47uF | 47u | electrolytic, supply; read from the schematic by eye | |
| ×1 | ? | ? | electrolytic on the Z reference, value not printed; read from the schematic by eye | |
| Diodes 1 | ||||
| ×4 | Diode | DIODE | no part number given: supply protection, MN3101 pin 1, JFET gate, LED string; read from the schematic by eye | |
| Transistors 2 | ||||
| ×7 | 2SC1815 | 2SC1815 | buffers, filter stages and flip-flop; one filter-stage transistor is unlabelled, assumed 2SC1815; read from the schematic by eye | |
| Q8 | ? | ? | JFET bypass switch, type not given; read from the schematic by eye | |
| ICs 4 | ||||
| IC1 | 4558D | 4558D | dual op amp; read from the schematic by eye | |
| ×1 | NE570N | NE570N | compander, both halves used; read from the schematic by eye | |
| ×1 | MN3005 | MN3005 | BBD; read from the schematic by eye | |
| ×1 | MN3101 | MN3101 | BBD clock; read from the schematic by eye | |
| Potentiometers 3 | ||||
| Repeat | B100K | B100k | Potentiometer | read from the schematic by eye |
| Mix | B100K | B100k | Potentiometer | read from the schematic by eye |
| Delay | B1M | B1M | Potentiometer | drawn '1MB'; read from the schematic by eye |
| Trimmers 2 | ||||
| ×1 | 50K | 50k | MN3005 bias; read from the schematic by eye | |
| ×2 | ? | ? | clock trim beside Delay and the gain trim above the 0.047 to Mix; no values printed; read from the schematic by eye | |
| LEDs 1 | ||||
| ×1 | LED | LED | effect indicator; read from the schematic by eye | |